`timescale 1ns / 1ps
 
module INSTMEM(
 
      input  [31:0] address,
 
      output [31:0] inst
 
    );
 
    wire [31:0] ram [0:18];
 
 
 
 assign ram[5'h00] = 32'b001000_00001_00001_0000000000000000;
 
//不写的码，仅占位用(andi R1 , R1 , 0x0000)
 
assign ram[5'h01] = 32'b001000_00001_00001_0001001000110100;
 
//addi R1 , R1 , 0x1234   
 
assign ram[5'h02] = 32'b001000_00010_00010_0001000100010001;
 
//addi R2 , R2 , 0x1111
 
 assign ram[5'h03] = 32'b000000_00001_00010_00011_00000_100000;
 
//add R3 , R1 , R2 0x2345
 
assign ram[5'h04] = 32'b000000_00001_00010_00100_00000_100010;
 
//sub R4 , R1 , R2 0x0123
 
assign ram[5'h05] = 32'b000000_00001_00010_00011_00000_100100;
 
//and R3 , R1 , R2  0x1010
 
assign ram[5'h06] = 32'b000000_00001_00010_00100_00000_100101;
 
//or R4 , R1 , R2 0x1335
 
assign ram[5'h07] = 32'b001100_00001_00101_0010001000100010;
 
//andi R5 , R1 , 0x2222
 
assign ram[5'h08] = 32'b001101_00001_00101_0011001100110011;
 
//ori R5 , R1 , 0x3333
 
assign ram[5'h09] = 32'b000010_00000000000000000000001100;
 
//j   跳转到beq行  0800000C
 
assign ram[5'h0a] = 32'b000000_00000_00010_00011_00100_000010;
 
//不用
 
assign ram[5'h0b] = 32'b000000_00000_00010_00011_00100_000011;
 
//不用
 
assign ram[5'h0c] = 32'b000100_00001_00011_0000000000000011;
 
//beq R1 , R2 , 3 不跳 10230003
 
assign ram[5'h0d] = 32'b000101_00001_00011_0000000000000010;
 
//bne R1 , R2 , 2 跳至sw行  14230002
 
assign ram[5'h0e] = 32'b001101_00001_00011_0000000011101111;
 
//不用
 
assign ram[5'h0f] = 32'b001110_00001_00011_0000000011101111;
 
//不用
 
assign ram[5'h10] = 32'b101011_00100_00101_0000000000000001;
 
//sw R5 , 1(R4)  AC850001 r5=r4=0x1335
 
assign ram[5'h11] = 32'b100011_00100_00110_0000000000000001;
 
// lw R6 , 1(R4)  8C860001
 
assign ram[5'h12] = 32'b000010_00000000000000000000000001;
 
//j 跳回开头  08000001
 
assign inst = ram[address[6:2]];
 
endmodule